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Design and implementation of an EPLD-based variable length coder for real time image compression applications

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2 Author(s)
Ramachandran, S. ; Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India ; Srinivasan, S.

This paper proposes an effective implementation of Variable Length Coder (VLC) for image compression using an Embedded Programmable Logic Device (EPLD) to meet the real time requirements. The scheme has features such as header information and color processing not found in earlier implementations. It has a throughput of 50 Mbps at 50 MHz clock rate. The design fits into just one piece of a commercially available EPLD and is capable of processing monochrome images of sizes up to 1024×768 pixels and color images of up to 67% of this size, both at the rate of 25 frames per second

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Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:1 )

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