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The design of a 1.5 V, 10-bit, 10 M samples/s low power pipelined analog-to-digital converter

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2 Author(s)
Jen-Shiun Chiang ; Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan ; Ming-Da Chiang

An experimental low-voltage low-power pipelined analog-to-digital converter is designed and presented in this paper. The power consumption is efficiently reduced by using switched operational amplifiers and dynamic comparators. This chip is designed in a 0.35 μm CMOS process. The core area occupies 1450 μm×1100 μm. The HSPICE simulation results show that the resolution of this design is 10-bit; the sampling rate is 10 MHz; the peak SNDR is 66 dB, and the power consumption is 15 mW at 1.5 V supply voltage

Published in:

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:1 )

Date of Conference:

2000