A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers

With the advent of the World Wide Web and the services on it, there is a strong demand for the nodes that make Internet routing with guaranteed speed and throughput. Current 40-channel WDM (Wavelength Division Multiplexing) has boosted a single 2.5 Gbps OC-48 link to 100 Gbps, so the requirement to make IPv4 (Internet Protocol version 4) routing table lookup is 100 MLPS (million lookups per second.) The emerging 96-channel WDM and 10 Gbps OC-192 fibers certainly demand much more. Previous works on fast IPv4 routing table lookup used indirect RAM indexing to CPU caching or CAM (Content Addressable Memory) to achieve a few or tens MLPS. Their theoretical best performances depend on the memory access speed and some of them are not extensible to accommodate the forthcoming IPv6. In this paper we describe a novel way to do this work with only a FPGA, and this approach, which utilizes the logic modeling and minimization techniques, promises a capability to make IPv4 and (IPv6) routing decisions in a pipelined fashion within only a FPGA CLB delay time