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Test set compaction algorithms for combinational circuits

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2 Author(s)
Hamzaoglu, I. ; Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA ; Patel, J.H.

This paper presents a new algorithm, essential fault reduction, for generating compact test sets for combinational circuits under the single stuck-at fault model, and a new heuristic for estimating the minimum single stuck-at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced automatic test pattern generation system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan versions of the ISCAS89 benchmark circuits

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:19 ,  Issue: 8 )