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On improving test quality of scan-based BIST

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3 Author(s)
Huan-Chih Tsai ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Kwang-Ting Cheng ; Bhawmik, S.

In this paper, we explore two techniques, under the existing scan-based built-in self-test (BIST) architectures, for improving the test quality with practically no additional overhead. The proposed techniques are an almost-full-scan BIST strategy and a general scan-based BIST test application scheme. We first demonstrate that under the scan-based BIST architecture, full scan may not result in the highest fault coverage (FC) and unscanning a small number of scan flip-flops may increase the BIST FC. We then present an algorithm for identifying those not-to-be-scanned flip-flops. We further show that the proposed general scan-based BIST test application scheme could also result in higher BIST FC and only requires a minor modification to the BIST controller. Experiments have been conducted using an industrial tool, psb2, on benchmark circuits to illustrate the effectiveness of the proposed techniques and algorithms. The results have demonstrated that both techniques are able to maximize the FC and reduce the test application time without additional test hardware compared to the conventional scan-based BIST architectures

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:19 ,  Issue: 8 )