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Transparency-based hierarchical test generation for modular RTL designs

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4 Author(s)
Makris, Y. ; Reliable Syst. Synthesis Lab., California Univ., San Diego, La Jolla, CA, USA ; Collins, J. ; Orailoglu, A. ; Vishakantaiah, P.

We discuss a novel hierarchical test generation methodology for RTL designs, based on the concept of modular transparency. We introduce the channel notion, a powerful mechanism that captures modular transparency in terms of bijection functions defined on variable bitwidth signal entities. Through a recursive search algorithm, transparency channels are further combined into reachability paths suitable for translating local test vectors for each module into global design test. A divide and conquer hierarchical test generation methodology is described, resulting in significant test generation time speed-up and comparable fault coverage and vector count to complete circuit gate-level ATPG

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Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:2 )

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