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MPEG-4 video bitstream structure analysis and its parsing architecture design

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5 Author(s)
Hao-Chieh Chang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Yung-Chi Chang ; Yuan-Bin Tsai ; Chih-Peng Fan
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In this paper, the hardware-oriented structure analysis and an efficient and flexible bitstream parser for MPEG-4 video are presented. The analysis of bitstream structure explores processing requirement and design constraint for bitstream-level processing. The proposed architecture is basically RAM-based that can be reconfigured for various applications. For high bitrate as about 40 Mbit/s, it needs only about 19 MIPS to parse the bitstream. The impact of the proposed architecture on MPEG-4 video is to enhance and extend the processing for bit domain translation and related real time applications

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Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:2 )

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