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A multiplier-free fixed-task digital CNN array for video segmentation system

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3 Author(s)
A. Paasio ; Lab. of Electron. & Inf. Technol., Turku Univ., Finland ; J. Paakkulainen ; J. Isoaho

In this paper an alternative approach is given for implementing a fixed template cellular nonlinear network processor. The new concept is based on calculations in the digital domain to achieve accuracy not easily available with analog circuitry. A particular task, namely a noise removal operation, is considered here. Simplifications to the integration update rule are introduced that make the hardware realization simple. Moreover, results are given where the number of iteration steps in the integration show the achieved accuracy in the processed image with different word lengths. The design of the processor cell is given in a block level and both the processing time and the size of the hardware realization of this topology are estimated

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Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:3 )

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