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A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems

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3 Author(s)
Doboli, A. ; Dept. of Electron. Comput. & Eng. Comput. Sci., Cincinnati Univ., OH, USA ; Dhanwada, N. ; Vemuri, R.

This paper presents a heuristic technique for automatically generating different architectures for an analog system. The AG iteratively produces various system net-lists as distinct implementations can realize the signal processing and flow in a system. Area and power for resulting net-lists are rapidly evaluated with High-Level Performance Estimator (HPE), a simplified estimation module. The AG algorithm is simple to implement. It does not require an extensive pattern library as traditional AG techniques do

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Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:3 )

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