By Topic

Interconnect layout macromodelling and simulation in high speed circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kaufmann, N. ; Groupement d''Interet Econ., OPTO+, Marcoussis, France ; Konczykowska, A.

This paper deals with the layout problems of VHSICs. It shows how parasitic influence of the interconnects on the global circuit performance can be selectively taken into account. The method is based on the layout extraction coupled with a model library of basic forms. Hierarchical symbolic analysis is proposed to create macromodels and speed up the calculation. An example of 40 Gb/s driver design illustrates the presented approach

Published in:

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:3 )

Date of Conference:

2000