Referenced Items are not available for this document.
This paper deals with the layout problems of VHSICs. It shows how parasitic influence of the interconnects on the global circuit performance can be selectively taken into account. The method is based on the layout extraction coupled with a model library of basic forms. Hierarchical symbolic analysis is proposed to create macromodels and speed up the calculation. An example of 40 Gb/s driver design illustrates the presented approach
Published in:
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
(Volume:3
)
Date of Conference: 2000
- Page(s):
- 125 - 128 vol.3
- Meeting Date :
- 28 May 2000-31 May 2000
- Print ISBN:
- 0-7803-5482-6
- INSPEC Accession Number:
- 6747948
- Conference Location :
- Geneva
- Digital Object Identifier :
- 10.1109/ISCAS.2000.856012
- Product Type:
- Conference Publications
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