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An analog BiCMOS integrated circuit for front-end RDS decoder

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6 Author(s)
A. Baschirotto ; Dipartimento di Elettronica, Pavia Univ., Italy ; M. Cassis ; P. Kirchlechner ; F. Montecchi
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An analog integrated front-end circuit for the RDS (Radio-Data-System) digital decoder is described. The core of the circuit is an 8th-order switched-capacitor (SC) bandpass filter at 57 kHz with linear-phase response in a 3 kHz bandwidth. A low-offset comparator provides the squared signal for the digital decoder. Antialiasing and smoothing filters are also included in the chip, as well as the clock generation for the SC section; few external components are required. Integrated in a high-performance BiCMOS technology, the circuit operates from a single 5-V supply and dissipates 45 mW. The die size is 5 mm2

Published in:

IEEE Transactions on Consumer Electronics  (Volume:37 ,  Issue: 3 )