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1 Author(s)
Parhami, B. ; California Univ., Santa Barbara, CA, USA

Designs of hardware voters are presented that can be easily pipelined to accommodate extremely high data rates. Design strategies for bit-voters and word-voters are described. Examples of resultant designs are given and each design is evaluated with respect to cost and performance. Both ordinary and generalized m-out-of-n voting, with arbitrary vote assigned to the inputs, are considered. Median voters can be synthesized by simple variants of the design methods. Using currently available technology, these designs can operate at speeds of many millions of votes per second. For majority bit-voters with small values of n, a multiplexer-based design method generally yields the best realizations while for larger values of n , designs based on selection networks tend to be most efficient. For word voters, cost-effective designs based on modified or augmented sorting networks are feasible. In either case, the rich theory developed for the analysis and synthesis of parallel/pipelined sorting networks directly benefits the design process

Published in:

Reliability, IEEE Transactions on  (Volume:40 ,  Issue: 3 )

Date of Publication:

Aug 1991

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