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Improved vein pattern extracting algorithm and its implementation

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5 Author(s)
Sang-Kyun Im ; ASIC Design Lab., Korea Univ., Seoul, South Korea ; Hyung-Man Park ; Soo-Won Kim ; Chang-Kyung Chung
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This paper proposes an improved vein pattern extracting algorithm which compensates the loss of vein patterns in the edge area, gives more enhanced and stabilized vein pattern information, and shows better performance than the existing algorithm. Also, the problem arising from the iterative nature of the filtering preprocess in the existing algorithm is solved by designing a filter that is processed only one time so that a fast recognition speed and reduced hardware complexity is obtained. The proposed algorithm is implemented with a FPGA (field programmable gate array) device and the FAR (false acceptance rate) shows five times batter than the existing algorithm and the recognition speed is measured to be 100 [ms/person].

Published in:

Consumer Electronics, 2000. ICCE. 2000 Digest of Technical Papers. International Conference on

Date of Conference:

13-15 June 2000