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The physical basis of the cold-FET method for extracting parasitic resistances and inductances is examined. A method to obtain the source resistance from the gate-current dependence of the FET Z parameters is used to analyze FETs with different gate lengths. Inductance results for FETs with different gate widths suggest that inductance extrinsic to the gate fingers is dominant, and models of the gate inductance support this. The effects that possible dependences of the parasitic-FET equivalent-circuit parameters (ECPs) on the gate and drain bias can have on the extracted intrinsic-FET parameters are discussed.