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Design of a high-speed packet switch with fine-grained quality-of-service guarantees

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2 Author(s)
Bhagwan, R. ; Center for Wireless Commun., California Univ., San Diego, La Jolla, CA, USA ; Bill Lin

We present a new input-queued switch architecture designed to support deadline-ordered scheduling at extremely high-speeds. In particular, deadline-ordered scheduling is enabled through a combination of hardware-based sorted priority queues called P-heaps and a round-robin crossbar scheduler. The priority queues are implemented using a novel scalable pipelined heap-based architecture. Using a 0.35 micron CMOS standard-cell technology, we demonstrate a 32-port switch capable of sustaining 10 Gb/s line rates

Published in:

Communications, 2000. ICC 2000. 2000 IEEE International Conference on  (Volume:3 )

Date of Conference:

2000