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Design for testability techniques for CMOS combinational gates

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4 Author(s)
G. Buonanno ; Dept. of Electron., Politecnico di Milano, Italy ; F. Lombardi ; D. Sciuto ; Y. -N. Shen

The design of easily testable CMOS combinational circuits is discussed. Two CMOS structured design techniques are presented. The novelty of this approach is the complete fault detection of single- and multiple-line stuck-at, transistor stuck-open, and stuck-on faults for combinational circuits. The test algorithm requires only minimal modifications to detect a large number of bridging faults. These techniques are both based on the addition of two transistors, a P-FET and an N-FET, which are placed in series between the P and N sections. In the first case (dynamic fully CMOS, DFCMOS), the transistors are controlled by a single input; in the other case (testable fully CMOS, TFCMOS), there is one input for each additional transistor. The test procedure is presented, and it is shown that multiple fault detection can be easily achieved

Published in:

IEEE Transactions on Instrumentation and Measurement  (Volume:40 ,  Issue: 4 )