By Topic

One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Mirza, A.R. ; Electron. Visions Inc., Phoenix, AZ, USA

The ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate is becoming a critical issue for a variety of semiconductor applications. For CMOS devices this technology will be applied for chip-scale packaging and also for advanced 3-D interconnect processes. In the microelectromechanical systems (MEMS) arena, accurate alignment of two silicon micromachined wafers enables the design of more advanced MEMS devices and aggressive die shrinks of existing products. In this paper we discuss the advantages and disadvantages of various substrate-to-substrate alignment techniques including infrared, through wafer via, inter-substrate optical and wafer backside alignment methods. We also report on a new approach to wafer-to-wafer alignment that relies on precision alignment positioning systems to register and align wafers with one micron or better precision. Test results from this wafer-to-wafer alignment system demonstrate that one micron alignment accuracy can be routinely obtained. This new wafer-level alignment and bonding technique is particularly well suited for high-volume manufacturing due to the long-term stability of the precision alignment positioning system. This paper gives a brief overview of some typical uses of aligned wafer-level bonding for chip-scale, 3-D interconnect and MEMS applications

Published in:

Electronic Components & Technology Conference, 2000. 2000 Proceedings. 50th

Date of Conference: