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A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching

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3 Author(s)
Chan-Hong Park ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Ook Kim ; Beomsup Kim

A 1.8 GHz phase-locked loop (PLL) with a self-calibration circuit implemented in 0.35 /spl mu/m CMOS process is presented. The calibration circuit continuously adjusts the delay mismatches among the delay cells in a ring-type voltage controlled oscillator (VCO) and automatically cancels the phase offsets in the multi-phase clock signals generated from the VCO. An edge-combining fractional-N frequency synthesizer with the self-calibrated PLL has been implemented and successfully eliminates -13 dBc fractional spur occurring owing to the delay mismatches in the VCO.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000