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A new architecture for phase-locked-loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching and high immunity of substrate noise. A prototype is designed for 1.5 V and consumes 30 mW. The total chip area is 0.9/spl times/1.1 mm/sup 2/. The settling time is less than 150 /spl mu/sec and the phase noise is -118 dBc/Hz at 600 KHz offset.