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A 200 MHz, 3 mW, 16-tap mixed-signal FIR filter

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2 Author(s)
Figueroa, M. ; Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA ; Diorio, C.

We have built a 16-tap, 7-bit, 200 MHz, mixed-signal FIR filter that consumes 3 mW at 3.3 V. The filter uses p-channel synapse transistors to store the tap coefficients; electron tunneling and hot-electron injection to modify the tap weights; digital registers for the delay line; and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap weights. The measured bandwidth is 225 MHz; the measured tap multiplier resolution is 7 bits at 200 MHz. The total die area is 0.13 mm/sup 2/; we can readily scale the design to higher bit resolutions and longer delay-lines.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000