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An 8-bit 125 MS/s CMOS folding ADC for Gigabit Ethernet LSI

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4 Author(s)
Kwangho Yoon ; Sch. of Electr. Eng., Seoul Nat. Univ., South Korea ; Jeongho Lee ; Deog-Kyoon Jeong ; Wonchan Kim

An 8-bit 125 MS/s CMOS folding ADC using an equalizing technique is presented, which reduces the settling time of the analog folding processor to obtain a higher sampling rate. The prototype chip, fabricated in a 0.35 /spl mu/m triple metal digital CMOS process, occupies an area of 0.8 mm/sup 2/ and consumes 110 mW achieving 6.4 effective bits for a Nyquist input signal.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000