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470 ps 64-bit parallel binary adder [for CPU chip]

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4 Author(s)
Jaehong Park ; Samsung Electron., Kyunggi-Do, South Korea ; Ngo, H.C. ; Silberman, J.A. ; Dhong, S.H.

This paper presents a fast 64-bit parallel carry look-ahead binary adder implemented in a 1 GHz research prototype 64-bit PowerPC microprocessor. Efficient use of dynamic compound gates enables implementation of the adder in just three stages of delayed reset dynamic logic. The computation uses only G (Generate) and P (Propagate), and the inverse of Carry is computed from G, P, and a strobe signal.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000