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A selective verify scheme for achieving a 5-MB/s program rate in 3-bit/cell flash memories

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5 Author(s)
Kurata, H. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Kobayashi, N. ; Kimura, K. ; Saeki, S.
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The demand for high density and high-speed programming in flash memories has grown because of audio- and video- storage applications. A multilevel technique is the most effective approach to improving memory density, but it requires precise control of a memory cell's Vth that doesn't degrade programming performance. To enable this, we have developed a selective verify scheme for high-speed programming based on simultaneous multilevel programming. A selective verify scheme with asymmetrical cell operation and two-bank operation makes 5-MB/s programming throughput in 3-bit/cell flash memories attainable.

Published in:
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference: 15-17 June 2000

Page(s):
166 - 167
Meeting Date :
15 Jun 2000-17 Jun 2000
Print ISBN:
0-7803-6309-4
INSPEC Accession Number:
6715290
Conference Location :
Honolulu, HI, USA
Digital Object Identifier :
10.1109/VLSIC.2000.852880
Product Type:
Conference Publications

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