By Topic

A 60 ns access 32 kByte 3-transistor flash for low power embedded applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Ikehashi, T. ; ULSI Device Eng. Lab., Toshiba Corp., Yokohama, Japan ; Noda, J. ; Imamiya, K. ; Ichikawa, M.
more authors

In this paper, we present a new memory, 3-transistor flash (3-Tr), which is suited to the embedded application. The memory cell has inherited low power the erase/program characteristic of the NAND flash. The cell size of the 32kByte 3-Tr flash, fabricated in a 0.4um NAND flash technology, is 4.36 /spl mu/m/sup 2/. This is about 1/8 of the EEPROM cell size having the same design rule. We also propose two circuit technologies, a low power sensing scheme and a double stage boosting scheme (DSB). The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during the program mode. It is also immune to a decrease of the supply voltage Vdd.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000