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A 2.5 V, 20 Gbyte/s 288 M packet-based DRAM with enhanced cell efficiency and noise immunity

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8 Author(s)
K. -H. Kyung ; Samsung Electron. Co. Ltd., Kyungki, South Korea ; H. -C. Lee ; K. -W. Song ; H. -S. Song
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Multimedia and multi-tasking computing systems demand high bandwidth and multi-bank DRAMs. To meet these requirements, several challenges regarding the chip size penalty and noise concerns associated with multi-I/O lines should be resolved. This paper describes a 2.5-V, 288-Mb DRAM with a 32-bank architecture achieving a peak bandwidth of 2.0 GB/s using both 500-MHz differential clocks and 18-I/O organization. This chip features (1) an area- and performance-efficient chip architecture with well-mixed high-speed interface circuits with DRAM peripheral circuits to increase the cell efficiency, (2) a multi-level controlled equalizing scheme and a distributed sense amplifier-driving scheme to enhance the DRAM core timing margin while digressing from the conventional sub-wordline driving scheme, having 352 cells per sub-wordline, (3) an area-efficient column redundancy scheme with multiple fuse-boxes instead of excessive spare memory cell arrays for the multi-I/O architecture, (4) a zero-DC current receiver with a counter kick-back coupling scheme to reduce the reference coupling noise, and (5) a PVT (power, voltage, time) insensitive current control scheme.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000