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A bit-line leakage compensation scheme for low-voltage SRAM's

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4 Author(s)
Agawa, K. ; Syst. ULSI Eng. Lab., Toshiba Corp., Kawasaki, Japan ; Hara, H. ; Takayanagi, T. ; Kuroda, T.

The bit-line leakage current of an SRAM, induced by transistor leakage at low V/sub DD/ and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. By this scheme, V/sub th/ can be lowered to 0.23 V/sub DD/ in a 0.07 /spl mu/m/1.0 V CMOS, as it was before, keeping V/sub th/ and delay scalability of the high-speed SRAM.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000