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Advanced SOI-MOSFETs with strained-Si channel for high speed CMOS-electron/hole mobility enhancement

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4 Author(s)
Mizuno, T. ; Adv. LSI Technol. Lab., Toshiba Corp., Yokohama, Japan ; Sugiyama, N. ; Satake, H. ; Takagi, S.

In this work, we propose strained-Si MOSFETs on double-layer SiGe films with different Ge contents as high performance p-MOSFETs. Actually, we demonstrate high hole mobility enhancement (45% against that in control-SOI MOSFETs and 30% against the universal mobility) in strained-SOI p-MOSFETs including double-hetero structures (Si/sub 0.82/Ge/sub 0.18//Si/sub 0.9/Ge/sub 0.1/) for the first time. Moreover, it is also demonstrated that the electron mobility in n-channel strained-SOI MOSFETs is enhanced by about 60%, using single SiGe layer with the Ge content of as low as 10%.

Published in:

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

13-15 June 2000