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A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

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37 Author(s)
Smeys, P. ; Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA ; McGahay, V. ; Yang, I. ; Adkisson, J.
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This paper describes a 1.2V high performance 0.13 /spl mu/m generation SOI technology. Aggressive ground-rules and a tungsten damascene local interconnect render the densest 6T SRAM reported to date with a cell area of 2.16 /spl mu/m/sup 2/. This is accomplished with 248nm lithography, using optical proximity correction and resolution enhancement techniques on all critical levels. Interconnect performance requirements are achieved by using up to 8 levels of Cu wiring and an advanced low-k interlevel dielectric.

Published in:

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

13-15 June 2000