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In this work a 0.20 /spl mu/m CMOS technology has been developed using copper-filled local interconnect and contact along with copper metallization. This technology is suitable for logic and SRAM applications. The presence of copper in close proximity to the gate oxide and source/drain regions does not induce any degradation to the transistor parameters. This study shows that copper, along with a robust diffusion barrier, can be used to fill local interconnect and contact holes without deteriorating device performance. In this technology, the minimum transistor is (0.27 /spl mu/m/spl times/0.15 /spl mu/m) with a gate pitch of 0.54 /spl mu/m and minimum metal pitch of 0.63 /spl mu/m.
Date of Conference: 13-15 June 2000