Referenced Items are not available for this document.
On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise
Published in:
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Date of Conference: 2000
- Page(s):
- 487 - 490
- Meeting Date :
- 21 May 2000-24 May 2000
- Print ISBN:
- 0-7803-5809-0
- INSPEC Accession Number:
- 6715420
- Conference Location :
- Orlando, FL
- Digital Object Identifier :
- 10.1109/CICC.2000.852714
- Product Type:
- Conference Publications
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