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Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video

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6 Author(s)
T. Kamemaru ; Inf. & Commun. Syst. Dev. Center, Mitsubishi Electr. Co. Ltd., Kamakura, Japan ; H. Ohira ; H. Suzuki ; K. Asano
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We have developed a media processor core for MPEG4/H.26X codec LSI, which realizes a real-time bi-directional encoding/decoding for CIF-resolution video at the frame rate of 30 fr/s. The core processor contains 6.3 M-transistors on only 14 mm silicon area and consumes 280 mW at 1.8 V. It features an MPEG-oriented hybrid architecture which incorporates a SIMD processor optimized for matrix-operation, a programmable VLC engine and two-dimensional multifunction DMA. Another features are a memory reduction approach by hardware assist and an operand isolation scheme, which realizes low cost and low power characteristics, respectively

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Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

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