By Topic

Dynamic current mode logic (DyCML), a new low-power high-performance logic family

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Allam, M.W. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Elmasry, M.I.

This paper presents a new logic style DyCML for low-power high-performance VLSI applications. The new logic family combines the speed, low supply voltage and noise immunity advantages of MCML circuits while achieving the low standby current and design simplicity features of dynamic circuits. Simulation results show that DyCML circuits are superior to CMOS and DCVS logic styles in terms of power and delay. A 16 bit DyCML Carry Look Ahead Adder (CLA) fabricated in 0.6 μm achieves a delay of 1.1 ns while dissipating 21.2 mW at 400 MHz

Published in:

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Date of Conference: