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Impact of technology scaling on CMOS RF devices and circuits

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4 Author(s)
E. Abou-Allam ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; T. Manku ; M. Ting ; M. S. Obrecht

In this paper, the RF/microwave performance of CMOS technology is examined as a function of the gate length. The following CMOS technologies are characterized and compared: 0.18 μm, 0.25 μm, 0.35 μm, 0.5 μm and 0.8 μm. The unity current gain frequency scales as one over the effective gate length. The minimum noise figure is less than 1.5 dB at 2.0 GHz for gate lengths less than 0.5 μm for both nMOS and pMOS transistors. The total device width required for conjugate noise matching is 400 μm and 50 μm for the 0.8 μm and 0.18 μm gate length, respectively. The current required for a 1.9 GHz cascode LNA is 15 mA and 2.7 mA for the 0.5 μm and 0.18 μm CMOS processes, respectively. This reduction in current is due to the fact that gm/Ids for a 0.18 μm process is 25 V-1 whereas it is equal to 5 V-1 for a 0.5 μm process. The advantage of using pMOS transistors is illustrated in a 1 volt RF front-end receiver

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Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

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