An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield

We have developed two schemes for improving access speed and reliability of a loadless four-transistor (4T) SRAM cell: a dual-layered twisted bit line, which reduces coupling capacitance between adjacent bit lines in order to achieve high-speed read/write operations; and triple-well shielding, which protects the memory cell from substrate noise and alpha particles. We incorporated these technologies in a 0.18-/spl mu/m CMOS process and fabricated a 16-Mb SRAM macro with a 1.9-/spl mu//sup 2/ memory cell. This macro fully functions at 400 MHz and has an access time of 2.35 ns.