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An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield

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12 Author(s)
Noda, K. ; ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan ; Matsui, K. ; Ito, S. ; Masuoka, S.
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We have developed two schemes for improving access speed and reliability of a loadless four-transistor (4T) SRAM cell: a dual-layered twisted bit line, which reduces coupling capacitance between adjacent bit lines in order to achieve high-speed read/write operations; and triple-well shielding, which protects the memory cell from substrate noise and alpha particles. We incorporated these technologies in a 0.18-μm CMOS process and fabricated a 16-Mb SRAM macro with a 1.9-μ2 memory cell. This macro fully functions at 400 MHz and has an access time of 2.35 ns

Published in:

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

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