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Low-power technique for on-chip memory using biased partitioning and access concentration

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2 Author(s)
Kawabe, N. ; Semicond. Co., Toshiba Corp., Kawasaki, Japan ; Usami, K.

In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different sizes of two sub-arrays by inserting transfer-gate into a bit-line. When a smaller array is accessed, the larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 codec LSI. Power consumption was reduced by 40%

Published in:

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Date of Conference:

2000