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Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA

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4 Author(s)
T. Pagarani ; Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA ; F. Kocan ; D. G. Saab ; J. A. Abraham

In this paper, we present different architectures and implementation for solving the general SATisfiability (SAT) problem on reconfigurable devices. In particular, we address the solution of this basic and important problem using multiple small FPGAs. Our approach utilizes partitioning and decomposition to map any large SAT problem on more than one small FPGA. First, a SAT problem is decomposed into several independent sub-problems. This way, all sub-problems may be solved on different FPGAs simultaneously. If any of the sub-problems can not fit on a single FPGA, then a second technique is used to divide the sub-problem into dependent parts. We compute the solution time and hardware resources for both approaches and also compare our results with the previously published results

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Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

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