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Applying placement-based synthesis for on-time system-on-a-chip design

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1 Author(s)
D. E. Lackey ; IBM Microelectron., Essex Junction, VT, USA

This paper examines the fundamental issues in timing closure, using present-day methodologies, for designs enabled by System-on-a-Chip (SOC) silicon technologies. Placement-based synthesis is proposed as a method to address these issues, and its benefits are contrasted against the problems of current methods. Finally, this paper discusses application of placement-based synthesis for optimum benefit in enabling on-schedule SOC design

Published in:

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

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