Referenced Items are not available for this document.
This paper examines the fundamental issues in timing closure, using present-day methodologies, for designs enabled by System-on-a-Chip (SOC) silicon technologies. Placement-based synthesis is proposed as a method to address these issues, and its benefits are contrasted against the problems of current methods. Finally, this paper discusses application of placement-based synthesis for optimum benefit in enabling on-schedule SOC design
Published in:
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Date of Conference: 2000
- Page(s):
- 121 - 124
- Meeting Date :
- 21 May 2000-24 May 2000
- Print ISBN:
- 0-7803-5809-0
- INSPEC Accession Number:
- 6715341
- Conference Location :
- Orlando, FL
- Digital Object Identifier :
- 10.1109/CICC.2000.852631
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
