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Simple method for limiting delay of optimised interleavers for turbo-codes

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3 Author(s)
Campanella, M. ; Dipt. di Ingegneria Elettrica, Palermo Univ., Italy ; Garbo, G. ; Mangione, S.

The authors propose a simple extension to a previously described iterative interleaver growth algorithm that enables the delay (and required memory) of designed interleavers to be halved with negligible performance loss. Low-power implementation of the finite state permutation engine is also described

Published in:

Electronics Letters  (Volume:36 ,  Issue: 14 )