By Topic

Analytical models for RTL power estimation of combinational and sequential circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
S. Gupta ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; F. N. Najm

In this paper, we propose a modeling technique that captures the dependence of the power dissipation of a (combinational or sequential) logic circuit on its input/output signal switching statistics. The resulting power macromodel consists of a quadratic or cubic equation in four variables, that can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process that uses a recursive least squares (RLS) algorithm by which such an equation-based model can be automatically built. This approach has been implemented and models have been built and tested for many combinational and sequential benchmark circuits

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:19 ,  Issue: 7 )