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Analytical models for RTL power estimation of combinational and sequential circuits

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2 Author(s)
Gupta, S. ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Najm, F.N.

In this paper, we propose a modeling technique that captures the dependence of the power dissipation of a (combinational or sequential) logic circuit on its input/output signal switching statistics. The resulting power macromodel consists of a quadratic or cubic equation in four variables, that can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process that uses a recursive least squares (RLS) algorithm by which such an equation-based model can be automatically built. This approach has been implemented and models have been built and tested for many combinational and sequential benchmark circuits

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:19 ,  Issue: 7 )

Date of Publication:

Jul 2000

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