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A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]

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3 Author(s)
Kasamsetty, K. ; Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA ; Ketkar, M. ; Sapatnekar, S.S.

This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. Since the delay under this model is a convex function, optimal sizing algorithms based on convex programming techniques are applied with the new delay model. Experimental results demonstrating the accuracy of proposed model are presented along with results of sizing various test circuits

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:19 ,  Issue: 7 )