Cart (Loading....) | Create Account
Close category search window
 

MSXmin: a modular multicast ATM packet switch with low delay and hardware complexity

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kannan, R. ; Dept. of Comput. Sci., Alabama Univ., Huntsville, AL, USA ; Ray, S.

We propose and analyze the architecture for a large-scale high-speed multicast switch called MSXmin. The hardware complexity of MSXmin is O(N log2 N) which compares favorably with existing architectures. Further, the internal latency of the MSXmin is O(log2 N) bits. While it is superior to the existing architectures in terms of the hardware complexity and the internal latency, it is comparable to other multicast switches in terms of the header overhead and translation table complexity. MSXmin is output buffered and based on the group knockout principle. Moreover, MSXmin is a dual-bit-controlled tree-based switch

Published in:

Networking, IEEE/ACM Transactions on  (Volume:8 ,  Issue: 3 )

Date of Publication:

Jun 2000

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.