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Linear tail-biting trellises, the square-root bound, and applications for Reed-Muller codes

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2 Author(s)
Shany, Y. ; Dept. of Electr. Eng., Tel Aviv Univ., Israel ; Be'ery, Y.

Linear tail-biting trellises for block codes are considered. By introducing the notions of subtrellis, merging interval, and sub-tail-biting trellis, some structural properties of linear tail-biting trellises are proved. It is shown that a linear tail-biting trellis always has a certain simple structure, the parallel-merged-cosets structure. A necessary condition required from a linear code in order to have a linear tail-biting trellis representation that achieves the square root bound is presented. Finally, the above condition is used to show that for r⩾2 and m⩾4r-1 or r⩾4 and r+3⩽m⩽[(4r+5)/3] the Reed-Muller code RM(r, m) under any bit order cannot be represented by a linear tail-biting trellis whose state complexity is half of that of the minimal (conventional) trellis for the code under the standard bit order

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Information Theory, IEEE Transactions on  (Volume:46 ,  Issue: 4 )