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A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs

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2 Author(s)
Huawen Jin ; Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA ; E. K. F. Lee

Timing errors in time-interleaved ADC's often generate undesirable spurs, and hence, degrade the spurious-free dynamic range (SFDR) of the ADC. In this paper, a digital-background calibration technique is proposed to minimize these effects. The proposed technique is based on digital interpolation, which estimates the correct output values from the output samples that suffer from timing errors. Since this technique requires an accurate estimation of the timing errors of the individual channels, a digital-background timing-error measurement technique is also proposed. Theoretical analysis, as well as simulation results, show that the calibration technique can greatly attenuate the spurs, and the SFDR can be significantly improved by 20-60 dB, depending on the digital hardware complexity and the ratio of sampling frequency and signal frequency. The major advantage of this technique is that all the calibration processes are carried out in the background using digital circuits, and only slight modification is required on the analog part of the ADC for obtaining a background estimation of the timing errors

Published in:

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:47 ,  Issue: 7 )