By Topic

Analysis of temperature effects on maximum power-efficiency of pass transistor logic networks in low-voltage CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Allam, A. ; Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada ; Khanafshar, O. ; Kwok, D. ; Rysinski, J.
more authors

This paper presents a comprehensive analysis of the effects of increased temperature on maximum power-efficiency (powerd-delay-product) of pass-transistor networks operating at low supply voltages using deep-submicron CMOS technology. Numerous gate functions, such as OR, NOR, AND, NAND, XOR and XNOR have been designed in double pass-transistor logic (DPL) and swing-restored pass-transistor logic (SRPL). These circuits have been investigated under various operating conditions: fanin, fanout, power supply voltage and temperature. The results show that increased temperature significantly affects the maximum power-efficiency operating point of these logic gates and consequently, the optimum operating point

Published in:

Electrical and Computer Engineering, 2000 Canadian Conference on  (Volume:1 )

Date of Conference: