Referenced Items are not available for this document.
A chip implementing the coordinate rotation digital computer (CORDIC) algorithm is described. It contains a 10-MHz 16-b fixed-point CORDIC arithmetic unit, 2-kb RAM, a controller, and input/output (I/O) registers. A modified data-path architecture allows cross-wire free data flow. The chip design involved development of optimized carry-select adders and a modified programmable-logic-array (PLA) cell layout, which allows speed increase in single-layer metal technology. The authors designed, fabricated, and tested a general-purpose fully parallel programmable CORDIC chip in CMOS technology and developed optimal iteration sequences
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:26
,
Issue:
9
)
Date of Publication: Sep 1991
- Page(s):
- 1317 - 1321
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 4026429
- Digital Object Identifier :
- 10.1109/4.84950
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Sep 1991
- Sponsored by :
- IEEE Solid-State Circuits Society
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