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Variable-taper CMOS buffers

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2 Author(s)
S. R. Vemuru ; Dept. of Electr. Eng., Toledo Univ., OH, USA ; A. R. Thorbjornsen

A variable-taper (VT) approach to buffer design in which the taper from one inverter stage to the next is a function of the position of the inverter within the buffer chain is proposed. Though the minimum delay obtained by using a VT buffer is about 15% more than the minimum delay obtained from conventional fixed-taper (FT) buffers, a small modification to the initial stages of the VT buffer reduces this difference to less than 2%. For similar delays, a VT buffer usually takes less area and consumes less power than an FT buffer

Published in:

IEEE Journal of Solid-State Circuits  (Volume:26 ,  Issue: 9 )