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Architecture and design of a 500-MHz gallium-arsenide processing element for a parallel supercomputer

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2 Author(s)
Fouts, D.J. ; Dept. of Electr. & Comput. Eng., US Naval Postgraduate Sch., Monterey, CA, USA ; Butner, S.E.

The design of the processing element of GASP, a GaAs supercomputer with a 500-MHz instruction issue rate and 1-GHz subsystem clocks, is presented. The novel, functionally modular, block data flow architecture of GASP is described. The architecture and design of a GASP processing element is then presented. The processing element (PE) is implemented in a hybrid semiconductor module with 152 custom GaAs ICs of eight different types. The effects of the implementation technology on both the system-level architecture and the PE design are discussed. SPICE simulations indicate that parts of the PE are capable of being clocked at 1 GHz, while the rest of the PE uses a 500-MHz clock. The architecture utilizes data flow techniques at a program block level, which allows efficient execution of parallel programs while maintaining reasonably good performance on sequential programs. A simulation study of the architecture indicates that an instruction execution rate of over 30,000 MIPS can be attained with 65 PEs

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Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 9 )