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Evolutionary graph generation system with symbolic verification for arithmetic circuit design

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3 Author(s)
Homma, N. ; Dept. of Syst. Inf. Sci., Tohoku Univ., Sendai, Japan ; Aoki, T. ; Higuchi, T.

A novel graph-based evolutionary optimisation technique for arithmetic circuit synthesis is proposed. Symbolic verification of the generated circuit structures is introduced to accelerate the time-consuming evolution process. The evolutionary graph generation (EGG) system based on the proposed technique can successfully generate the optimal 16-bit constant-coefficient multiplier within ∼2.2 h.

Published in:

Electronics Letters  (Volume:36 ,  Issue: 11 )

Date of Publication:

25 May 2000

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