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Arithmetic-oriented multiple-valued logic-in-memory VLSI based on current-mode logic

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3 Author(s)
Kaeriyama, S. ; Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan ; Hanyu, T. ; Kameyama, M.

A new logic-in-memory architecture, in which storage elements are distributed over a current-mode logic-circuit plane by the use of floating-gate MOS transistors, is proposed to realize a compact arithmetic VLSI system. Since not only a storage function but also a voltage-mode linear summation and a voltage-to-current conversion are merged into a single floating-gate MOS transistor, the logic-in-memory VLSI becomes very compact with a high-performance capability. As an example, it is demonstrated that the effective chip area of the proposed four-valued current-mode full adder is reduced to 5% under the same switching speed in comparison with the corresponding binary CMOS implementation

Published in:

Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on

Date of Conference:

2000

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